苏州市“员工进院校--千名优秀青年职工技能提升行动”政府指定项目

“DFT Compiler 1”培养课程简介

本课程由苏州中科集成电路设计中心和Synopsys公司联合面向苏州地区企业推出。苏州市企业在职工程师参加此课程，并完成相关考核，将有机会获得政府对项目培训费用的补助。

课程内容及时间安排

Overview

In this workshop, you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. The workshop will show you how to analyze the reported data to identify common DFT violations and then fix the original RTL design.

The class explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length, and reusing functional pins for scan testing; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage.

Objectives

At the end of this workshop the student should be able to:

· Define the test protocol for a design and customize the initialization sequence, if needed

· Perform DFT checks at both the RTL and gate levels

· State common design constructs that cause typical DFT violations

· Automatically correct certain DFT violations at the gate level using AutoFix

· Insert scan to achieve well-balanced top-level scan chains and other scan design requirements

· Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and place & route.

· Implement Rapid Scan Synthesis (RSS) in a top-down scan insertion flow achieving well-balanced scan chains

· Modify a bottom-up scan insertion script for full gate-level designs to use test models/ILMs with RSS and run it

· Preview top-level chain balance using test models/ILMs after block-level scan insertion and revise block-level scan architecture as needed to improve top-level scan chain balance.

· Modify a scan insertion script to include DFT-MAX Adaptive Scan compression

Audience Profile

Design and Test engineers who need to identify and fix DFT violations in their RTL or gate-level designs, insert scan into multi-million-gate SoCs, and export design files to ATPG and P&R tools

Prerequisites

There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision, and with writing Synopsys Tcl scripts is useful, but not required.

Course Outline

Day 1

· Introduction to Scan Testing

· DFT Compiler Flows

· DFT Compiler Setup

· Test Protocol

· DFT Design Rule Checks

Day 2

· DFT DRC GUI Debug

· DRC Fixing

· Top-Down Scan Insertion

Day 3

· Exporting Files

· High Capacity DFT Flows

· Multi-Mode DFT

· DFT MAX

Synopsys Tools Used

· DFT Compiler 2010.03-SP3

· Design Vision 2010.03-SP3

· Design Compiler 2010.03-SP3

· TetraMAX 2010.03-SP3

Time : 9:30 -12:00 13:00-17:00

师资情况介绍

尤国强

西北工业大学硕士毕业，Synopsys全球技术支持中心资深技术支持工程师，主要支持前端实现工具，包括DC,PT,DFTC,Tetramax等等，Synopsys全球技术支持中心中国区前端实现工具产品线team leader. 有超过16年数字集成电路前端设计和实现以及技术支持经验，曾任职于多家著名集成电路设计公司，包括中兴，华为，朗讯贝尔实验室等等。在Synopsys任职超过8年半，经验丰富。多次在Synopsys北京/上海/深圳培训中心以及北京/深圳/珠海/大连等地ICC成功主讲各种Synopsys前端工具及流程相关用户培训，学员口碑极佳。

申报条件

具有相关专业大专及以上学历，并在市区（含园区、新区）工作已建立稳定的劳动关系的企业在职工程师、项目经理等（报名时需提供相应证明材料复印件）。

课程时间及费用

课程时间：2011年3月2日-4日。课程费用2300元/人（其中，可享受政府补助1800元/人，并可免费参加2月23日的IC Compiler 2培训课程），费用包括考证费及教材费、培训费。

课程地点

苏州中科集成电路设计中心（苏州工业园区集成电路人才公共实训基地）培训教室：金鸡湖大道1355号国际科技园二期E401。

证书及考证

申报政府补贴学员必须通过政府主管部门组织的考试，考试合格将获得国家职业资格证书。

报名方式

单位或个人携带以下材料到苏州中科集成电路设计中心（苏州工业园区集成电路人才实训基地）报名。

报名地点：苏州工业园区金鸡湖大道1355号（原机场路）国际科技园二期E301；

联系人：邹老师 62889031 zoull@szicc.com.cn

报名材料：身份证、学历/学位证书、劳动合同、户口本（苏州市常住户口需提供）复印件，一寸近照4张。